The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for contacting a fin-type field-effect transistor (FinFET) and methods for fabricating a structure for contacting a FinFET.
A FinFET is a non-planar device structure for a field-effect transistor that is capable of being more densely packed in an integrated circuit than planar field-effect transistors. A FinFET includes one or more fins of semiconductor material and an overlapping gate electrode that intersects a channel within each fin. The channel in each fin is located between heavily-doped source/drain regions formed in fin sections that are not covered by the gate electrode. The fin dimensions and the number of fins determine the effective channel width of the FinFET.
Contacts, often referred to as CA contacts, are formed in order to make electrical connections to the source/drain regions of the FinFET. The source/drain regions and their contacts must remain electrically insulated from the gate electrode and its contact in order to ensure the functionality of the FinFET. Otherwise, a short circuit can occur that may damage the FinFET. The CA contacts are typically formed in contact holes that are etched in a interlayer dielectric and, as a result, are surrounded by the insulating material of the interlayer dielectric.
In a self-aligned contact (SAC) process, the contact hole for a CA contact can partially overlap with the gate conductor, which requires the gate conductor to be capped and clad by spacers to avoid shorting. As technology nodes advance, the space available between adjacent gates decreases with decreasing pitch. The decreased spacing increases the difficulty in contacting the source/drain regions without inflicting damage to the gate electrode when etching contact holes in the interlayer dielectric.